Wide bandgap semiconductor device including transistor cells and compensation structure

ABSTRACT

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

CROSS-REFERENCE TO RELATED APPLICATION

This Utility patent application claims priority to German PatentApplication No. 10 2016 104 256.0, filed Mar. 9, 2016; which isincorporated herein by reference.

BACKGROUND

SiC MOSFETs (silicon carbide metal oxide semiconductor field effecttransistors) exhibit lower on-state resistance at high temperatures,lower switching losses and lower leakage currents compared toconventional silicon MOSFETs. The gate dielectric of SiC MOSFETs may beeconomically formed by thermally oxidizing the SiC substrate to obtain alayer of silicon oxide SiO₂, wherein carbon residuals may result in thata density of interface states at the SiO₂/SiC interface is more than twoorders of magnitude higher than at typical Si/SiO₂ interfaces. Theinterface states, which may also develop at interfaces between SiC anddeposited silicon oxide, may adversely affect the performance ofSiC-MOSFETs.

It is desirable to provide wide bandgap semiconductor devices witheconomically formed gate dielectrics and with stable andtemperature-independent device parameters.

SUMMARY

According to an embodiment, a semiconductor device includes transistorcells formed in a semiconductor portion of a wide bandgap material. Thetransistor cells are electrically connected to a gate terminal, a sourceterminal, and a drain terminal. A compensation structure is electricallyconnected with the gate terminal and with at least one of the sourceterminal and the drain terminal. An effective capacitance of thecompensation structure has a temperature coefficient at least partlycompensating for a temperature coefficient of a ratio between agate-to-drain capacitance and a gate-to-source capacitance of thetransistor cells.

According to another embodiment, a semiconductor device includestransistor cells in a semiconductor portion of silicon carbide. Thetransistor cells are electrically connected to a gate metallization, asource electrode and a drain electrode. A doped region in thesemiconductor region is electrically connected to the source electrode.A resistance of the doped region has a negative temperature coefficient.An interlayer dielectric separates the gate metallization from the dopedregion. A drain structure in the semiconductor portion electricallyconnects the transistor cells with the drain electrode and forms a pnjunction with the doped region.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description and onviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification. The drawings illustrate the embodiments ofthe present invention and together with the description serve to explainprinciples of the invention. Other embodiments of the invention andintended advantages will be readily appreciated as they become betterunderstood by reference to the following detailed description.

FIG. 1A is an equivalent circuit diagram of a semiconductor device witha compensation structure providing a capacitance with a temperaturecoefficient compensating a negative temperature coefficient of agate-to-source capacitance of transistor cells according to anembodiment with the compensation structure connected between drain andgate terminal.

FIG. 1B is an equivalent circuit diagram of a semiconductor device witha compensation structure providing a capacitance with a temperaturecoefficient compensating a negative temperature coefficient of agate-to-source capacitance of transistor cells according to anembodiment with the compensation structure connected between gate andsource terminal.

FIG. 2 is an equivalent circuit diagram of a semiconductor deviceincluding a compensation structure according to an embodiment with athermistor structure with negative temperature coefficient.

FIG. 3A is a schematic diagram illustrating interface state densityalong an SiC/SiO₂ interface for discussing background useful forunderstanding of the embodiments.

FIG. 3B is a schematic diagram illustrating a relationship between gatecharge and gate-to-source voltage as a function of temperature in a SiCsemiconductor device for discussing background useful for understandingof the embodiments.

FIG. 3C is a schematic diagram illustrating a relationship betweendrain-to-source capacitance and drain-to-source voltage as a function oftemperature for a SiC semiconductor device for discussing backgrounduseful for understanding of the embodiments.

FIG. 4A is a schematic vertical cross-sectional view of a portion of asemiconductor device according to an embodiment including a compensationstructure based on a doped region with a resistivity with negativetemperature coefficient.

FIG. 4B is a schematic diagram showing the resistivity of a doped regioncontaining aluminum as a function of reciprocal temperature.

FIG. 5A is a schematic diagram for illustrating a relationship betweendrain-to-gate capacitance and drain-to-source voltage as a function oftemperature for a semiconductor device according to the embodiments.

FIG. 5B is a schematic diagram illustrating a relationship between gatecharge and gate-to-source voltage as a function of temperature for asemiconductor device according to the embodiments.

FIG. 6A is a schematic vertical cross-sectional view of a portion of aSiC MOSFET according to an embodiment concerning a layout withasymmetric transistor cells.

FIG. 6B is a schematic plan view of the semiconductor device portion ofFIG. 6A.

FIG. 7 is a schematic plan view of a semiconductor device in accordancewith an embodiment related to a compensation structure formed around agate pad.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and in which are shownby way of illustrations specific embodiments in which the invention maybe practiced. It is to be understood that other embodiments may beutilized and structural or logical changes may be made without departingfrom the scope of the present invention. For example, featuresillustrated or described for one embodiment can be used on or inconjunction with other embodiments to yield yet a further embodiment. Itis intended that the present invention includes such modifications andvariations. The examples are described using specific language, whichshould not be construed as limiting the scope of the appending claims.The drawings are not scaled and are for illustrative purposes only.Corresponding elements are designated by the same reference signs in thedifferent drawings if not stated otherwise.

The terms “having”, “containing”, “including”, “comprising” and the likeare open, and the terms indicate the presence of stated structures,elements or features but do not preclude additional elements orfeatures. The articles “a”, “an” and “the” are intended to include theplural as well as the singular, unless the context clearly indicatesotherwise.

The term “electrically connected” describes a permanent low-ohmicconnection between electrically connected elements, for example a directcontact between the concerned elements or a low-ohmic connection througha metal and/or a highly doped semiconductor. The term “electricallycoupled” includes that one or more intervening element(s) adapted forsignal transmission may be provided between the electrically coupledelements, for example elements that are controllable to temporarilyprovide a low-ohmic connection in a first state and a high-ohmicelectric decoupling in a second state.

The Figures illustrate relative doping concentrations by indicating “−”or “+” next to the doping type “n” or “p”. For example, “n-” means adoping concentration which is lower than the doping concentration of an“n”-doping region while an “n+”-doping region has a higher dopingconcentration than an “n”-doping region. Doping regions of the samerelative doping concentration do not necessarily have the same absolutedoping concentration. For example, two different “n”-doping regions mayhave the same or different absolute doping concentrations.

FIG. 1A refers to a semiconductor device 500 including a transistor cellarrangement 510 with a plurality of transistor cells electricallyconnected in parallel. The semiconductor device 500 may be or mayinclude an IGFET (insulated gate field effect transistor), for examplean MOSFET in the usual meaning including FETs with metal gates as wellas FETs with semiconducting gates, e.g., from doped polycrystallinesilicon or amorphous silicon, an IGBT (insulated gate bipolartransistor) or an MCD (MOS controlled diode), by way of example. Thetransistor cells TC may be field effect transistor cells, e.g., fieldeffect transistor cells of the enhancement type.

The semiconductor device 500 is based on a semiconductor portion from awide bandgap semiconductor with a bandgap of at least 2.0 eV at atemperature of 300 K. For example, the semiconductor material of thesemiconductor portion is silicon carbide of the 4H polytype (4H-SiC)with a bandgap of 3.21 eV at 300 K.

The equivalent circuit diagram of the transistor cell arrangement 510may include a capacitance-free transistor 440, which may be, forexample, an IGFET of the enhancement type. A capacitance C_(gd)(gate-to-drain capacitance) 430 is effective between a drain and a gateof the transistor cell arrangement 510. A capacitance C_(gs)(gate-to-source capacitance) 410 is effective between the gate and thesource. A C_(ds) (drain-to-source capacitance) 420 is effective betweenthe drain and the source.

The capacitance-free transistor 440 is characterized, inter alia, by athreshold voltage charge Q_(th) defining the amount of charge necessaryfor lifting the potential at the gate of the capacitance-free transistor440 to a threshold voltage at which a load current path between thedrain and source of the capacitance-free transistor 440 becomesconductive. With increasing temperature less interface states along aninterface between a gate dielectric of the transistor cells and thesemiconductor portion remain electrically active such that the thresholdvoltage charge Q_(th) decreases.

A Miller charge loading C_(gd) 430 may remain unaffected or may alsodecrease to some degree. But the reduction of the threshold voltagecharge Q_(th) is significantly greater than any potential reduction ofthe Miller charge Q_(gd) such that a ratio Q_(gd)/Q_(th) has a positivetemperature coefficient. Any change of a ratio between the Miller chargeQ_(gd) and the threshold voltage charge Q_(th) significantly impactsdevice performance as regards unintentional turn-on and unintentionaloscillations.

Typically, the ratio Q_(gd)/Q_(th) affects the probability for that theSiC MOSFET unintentionally turns on when voltage peaks, which may begenerated during turn-off of the SiC MOSFET, are coupled to the gateinput through the Miller capacitance C_(gd). The greater the Millercapacitance C_(gd) is in relation to C_(gs), the higher is theprobability and the risk that the SiC MOSFET unintentional turns on.Unintentional turn-on decreases the efficiency of a switching circuitincluding the SiC MOSFET. Where the SiC MOSFET is a high-side switch ora low-side switch in a half-bridge circuit, a short-circuit conditionwith both switches turned on may occur. On the other hand, withdecreasing ratio Q_(gd)/Q_(th) the probability for triggering undesiredoscillations in the application increases. It follows that SiC MOSFETsbehave differently at different temperatures. Depending on the design ofthe SiC MOSFET either the risk for unintentional turn-on is high at anupper end of the nominal operational temperature range or the risk ofunintentional oscillations is high at the lower end of the nominaloperational temperature range.

A compensation structure 450 is electrically connected with the gateterminal G and at least one of the source terminal S and the drainterminal D of the semiconductor device 500. An effective capacitance ofthe compensation structure 450 is charged with a compensation chargeQ_(cmp). The effective capacitance of the compensation structure 450 isprovided with a temperature coefficient at least partly compensating forthe positive temperature coefficient of Q_(gd)/Q_(th). In other words,the temperature coefficient of the effective capacitance of thecompensation structure 450 compensates the temperature dependency of theratio C_(gd)/C_(gs) such that device parameters influenced by the ratioC_(gd)/C_(gs) remain more stable across the total operationaltemperature range than without the compensation structure 450.

In FIG. 1A a first capacitive structure 451, which is electricallyconnected between the drain terminal D and the gate terminal G,represents the effective capacitance of the compensation structure 450.The effective capacitance of the compensation structure 450 is providedwith a negative temperature coefficient. With increasing temperatureless compensation charge Q_(cmp) loads the effective capacitance of thecompensation structure 450. The negative temperature coefficient ofQ_(cmp) is selected such that the ratio (Q_(gd)+Q_(cmp))/Q_(th) betweenthe sum of the Miller charge Q_(gd) and the compensation charge Q_(cmp)on the one hand and the threshold voltage charge Q_(th) on the otherhand is approximately constant within the operational temperature rangethe semiconductor device 500 is specified for. The negative temperaturecoefficient of the compensation structure 450 in thedrain-to-gate-branch at least partially compensates the negativetemperature coefficient of the threshold voltage charge Q_(th) withinthe operational temperature range.

In FIG. 1B a second capacitive structure 452, which is electricallyconnected between the gate terminal G and the source terminal S,represents the effective capacitance of the compensation structure 450.The effective capacitance of the compensation structure 450 is providedwith a positive temperature coefficient. With increasing temperaturemore compensation charge Q_(cmp) loads the effective capacitance of thecompensation structure 450. The positive temperature coefficient ofQ_(cmp) is selected such that the ratio Q_(gd)/(Q_(th)+Q_(cmp)) betweenMiller charge Q_(gd) and the sum of the threshold voltage charge Q_(th)and the compensation charge Q_(cmp) is approximately constant within theoperational temperature range the semiconductor device 500 is specifiedfor. The positive temperature coefficient of the compensation structure450 in the gate-to-source-branch at least partially compensates thenegative temperature coefficient of the threshold voltage charge Q_(th)within the operational temperature range. The embodiments of FIGS. 1Aand 1B may be combined with each other.

In FIG. 2 the compensation structure 450 includes a first capacitivestructure 451 and a second capacitive structure 452 electricallyconnected in series between the drain terminal D and the gate terminalG. A thermistor structure 456 with negative temperature coefficient iselectrically connected between the source terminal S and a connectionnode 455 between the first and second capacitive structures 451, 452.

When the resistance of the thermistor structure 456 is high, a voltagedrop across the thermistor structure 456 is comparatively high and theseries connection of the first and second capacitive structures 451, 452is electrically arranged mainly in parallel with C_(gd) such that thetotal capacitance between drain and gate is high. In addition, thesecond capacitive structure 452 is highly decoupled from the sourceterminal S such that the second capacitive structure 452 contributesonly to a low degree to a total capacitance between the gate terminal Gand the source terminal S.

With increasing temperature the resistance of the thermistor structure456 decreases and the voltage drop across the thermistor structure 456gets smaller such that during switching operation an increasing portionof the load current loads the second capacitive structure 452 as acapacitance parallel to C_(gs). With increasing temperature the secondcapacitive structure 452 increasingly contributes to the total capacityC_(gs). In other words, the thermistor structure 456 and the secondcapacitive structure 452 form a compensation structure 450 with aneffective capacitance between the gate terminal G and the sourceterminal S, wherein the effective capacitance has a positive temperaturecoefficient as discussed with reference to FIG. 1B.

In addition, with decreasing resistance of the thermistor structure 456the first capacitive structure 451 gets better coupled to the sourceterminal S, whereas a degree of coupling with the gate terminal Gdecreases. The first capacitive structure 451 increasingly turns into acapacitance effective between the drain terminal D and the sourceterminal S and decreasingly contributes to the overall gate-to-draincapacitance C_(gd). In other words, the first capacitive structure 451and the thermistor structure 456 form a compensation structure 450 withan effective capacitance between the drain terminal D and the gateterminal G, wherein the effective capacitance has a negative temperaturecoefficient as discussed with reference to FIG. 1A. Device parametersrelated to the ratio Q_(gd)/Q_(th) are more stable in a widertemperature range.

The right hand side of FIG. 3A shows an electronic band structure of abandgap material. An upper edge Ev of the valence band 610 representsthe highest energy of electrons present in the bandgap material atabsolute zero temperature. The lower edge Ec of the conduction band 620is the lowest energy level of vacant electronic states in the bandgapmaterial. Within the bandgap 615 between Ev and Ec typically no vacantelectron states exist.

The left hand side of FIG. 3A shows the density of interfaces statesD_(it) along an SiC/SiO₂ interface, wherein the interface states maymainly result from excess carbon atoms. The energy levels of theinterface states are adjusted to the electronic band structure of thebandgap material. The interface states represent energy levels forelectrons and are effective as acceptor states which are negativelycharged if occupied with electrons.

In case an IGFET with a gate electrode, which controls an MOS channel inan SiC crystal, includes a gate dielectric with an SiC/SiO₂ interface,the number of such interface states affect the threshold voltage.Namely, the less interface states exist within the bandgap 615, thelower is a negative voltage bias induced by the electrons occupying theinterface states at the gate dielectric, the lower is a thresholdvoltage V_(th) that suffices for opening the MOS channel in the SiCcrystal, and the lower is the threshold voltage charge Q_(th).

At a temperature Tx=300 K a great portion of the interface state densityD_(it) distribution overlaps the bandgap 615. With increasingtemperature the lower edge Ec of the conduction band 620 drops and asmaller portion of the interface state density D_(it) distributionoverlaps the bandgap 615 at a temperature Ty>Tx. Threshold voltageV_(th) as well as threshold charge Q_(th) drop accordingly.

The following FIGS. 3B and 3C refer to a simplified model of transistorcells and discount effects of other structures such as terminationconstructions and gate connections, e.g., gate pads.

In FIG. 3B line 701 plots V_(GS) as a function of the gate charge Q_(g)at a temperature T1=−40° C., line 702 at T2=25° C. and line 703 atT3=100° C. Bends between steeper portions of the lines 701, 702, 703 onthe left hand side and less steep portions at the right hand sideindicate a gate-to-source voltage V₁ and a gate charge Q₁ at which theopening MOS channel significantly affects the V_(GS)/Q_(g)characteristic. A change of V₁ with temperature indicates an analogouschange of the threshold voltage V_(th) with temperature wherein thethreshold voltage V_(th) given in data sheets is typically defined for astate in which the MOS channel conducts a given drain current.Accordingly, the threshold charge Q_(th) varies with Q₁. A decreasing V₁results in a drop of the threshold charge Q_(th) with increasingtemperature indicating a decreasing presence of effective interfacestates in the bandgap.

The length of the Miller Plateaus represented by the projection of theless steep portions of lines 701, 702, 703 onto the abscissa andrepresenting Q_(gd) does not change or changes only to a very lowdegree, thereby indicating that Q_(gd) is approximately stable over thepertinent temperature range.

In addition, in FIG. 3C line 711 plots C_(gd) as a function of thedrain-to-source voltage V_(DS) at a temperature T1=−40° C., line 712 atT2=25° C. and line 713 at T3=100° C. For a given V_(DS), also FIG. 3Cshows that C_(gd) and Q_(gd) do not change significantly withtemperature. As a consequence of C_(gd) being more stable than Q_(th),the ratios Q_(gd)/Q_(th) and C_(gd)/C_(gs) change with temperature.

As discussed above, conventional SiC MOSFETs with gate dielectricsformed by thermal oxidation or deposition of silicon oxide behavedifferently at different temperatures, wherein depending on the designof the SiC MOSFET either the risk for unintentional turn-on is high atan upper end of the nominal operational temperature range or the risk ofunintentional oscillations is high at the lower end of the nominaloperational temperature range.

By contrast, the compensation structures 450 as described, e.g., withreference to FIGS. 1A, 1B and 2 compensate for effects resulting from adrop of the threshold charge Q_(th) with increasing temperature suchthat the SiC MOSFET has both a low risk of unintentional turn-on and alow occurrence of oscillations across the whole operational temperaturerange.

The compensation structure 450 of FIGS. 1A, 1B and 2 may be realizedoutside a housing of the semiconductor device 500 or may be integratedin and/or on the same semiconductor portion in which the transistorfunctionality is realized. The compensation structure 450 may includededicated structures serving only for compensating the temperature driftof the ratio Q_(gd)/Q_(th). According to another embodiment, thecompensation structure 450 may include elements serving also otherpurposes.

The semiconductor device 500 of FIG. 4A uses a portion of a gatemetallization 330, which may be a gate pad or a gate connection line,e.g., a gate runner, a gate finger or a gate ring as a first electrodeof the first capacitive structure 451 of FIG. 2.

The semiconductor device 500 includes transistor cells formed in asemiconductor portion 100 and may be or may include an IGFET, forexample an MOSFET, an IGBT or an MCD. The semiconductor portion 100 isfrom crystalline wide bandgap semiconductor material such as SiC, forexample 4H-SiC.

At a front side the semiconductor portion 100 has a first surface 101which may include coplanar surface sections. The first surface 101 maycoincide with a main crystal plane or may be tilted to a main crystalplane by an off-axis angle, which absolute value may be at least 2° andat most 12°, e.g., about 4°. According to an embodiment, the firstsurface 101 may be serrated and includes parallel first surface sectionsshifted to each other and tilted to a horizontal plane as well as secondsurface sections tilted to the first surface sections and connecting thefirst surface sections such that cross-sectional line of the serratedfirst surface 101 approximates a saw-tooth line.

On the back of the semiconductor portion 100 an opposite second surface102 may extend parallel to the first surface 101. A distance between thefirst surface 101 at the front and a second surface 102 on the back isrelated to a nominal blocking capability of the semiconductor device500. A total thickness of the semiconductor portion 100 between thefirst and second surfaces 101, 102 may be in the range of severalhundred nm to several hundred m. The normal to the first surface 101defines a vertical direction and directions parallel to the firstsurface 101 are horizontal directions.

The semiconductor portion 100 includes a doped region 180 which iselectrically connected to a source electrode 310, wherein the dopedregion 180 may be connected to the source electrode 310 on one side ofthe gate metallization 330 or on opposite sides of the gatemetallization 330. The doped region 180 may directly adjoin to the firstsurface 101 or may be spaced from the first surface 101, wherein one ormore unipolar homojunctions or pn junctions may be formed between thefirst surface 101 and the doped region 180. A resistivity of at least aportion the doped region 180 has a negative temperature coefficient.According to an embodiment, the whole doped region 180 or a portion ofthe doped region 180 contains aluminum (Al) atoms at a density in arange from at least 5E17 cm⁻³ up to 1E19 cm⁻³, by way of example. Inaddition to aluminum, the doped region 180 may include further dopants,for example boron (B) atoms. The doped region 180 forms a thermistorstructure 456 as described with reference to FIG. 2.

A drain structure 120 forms a pn junction pnx with the doped region 180and may separate the doped region 180 from a drain electrode 320 at theback. The drain structure 120 may include at least a heavily dopedcontact layer forming an ohmic contact with a drain electrode 320directly adjoining to the second surface 102 and a lightly doped driftzone between the heavily doped contact layer and the pn junction pnx.

A portion of an interlayer dielectric 210 separates the gatemetallization 330 from the semiconductor portion 100. The interlayerdielectric 210 may include one or more dielectric layers from siliconoxide, silicon nitride, silicon oxynitride, doped or undoped silicateglass, for example BSG (boron silicate glass), PSG (phosphorus silicateglass), BPSG (boron phosphorus silicate glass), FSG (fluorosilicateglass) or a spin-on glass, by way of example. At least a portion of thegate metallization 330 is in a vertical projection of at least a portionof the doped region 180 containing Al. The gate metallization 330 andthe doped region 180 form the electrodes of a first capacitive structure451 as described in FIG. 2.

The doped region 180 and the drain structure 120 form electrodes of thesecond capacitive structure 452 of FIG. 2, wherein the capacitance ofthe second capacitive structure 452 is given by the junction capacitanceof the pn junction pnx between the doped region 180 and the drainstructure 120.

The resistivity of the doped region 180 has a negative temperaturecoefficient. At low operation temperatures, the resistance of the dopedregion 180 is high and the resulting lateral voltage drop across thedoped region 180 in direction of the center axis of the gatemetallization 330 is comparatively high such that capacitive couplingbetween the gate metallization 330 and the drain electrode 320 is high.With increasing temperature an increasing portion of a current thatcharges the junction capacitance of the pn junction pnx flows to thesource electrode 310 such that the doped region 180 increasingly shieldsthe gate metallization 330 against the drain electrode 320. Theeffective capacitance between gate metallization 330 and drain electrode320 drops with increasing temperature.

In SiC semiconductor devices the chip area is significantly smaller thanin silicon devices such that the contribution of the gate metallization330 to the total C_(gd) is comparatively high and a comparatively smallchange of the contribution of the gate metallization 330 to the totalC_(gd) suffices to compensate for the change of the threshold potentialcharge Q_(th).

FIG. 4B schematically shows the temperature dependency of the resistanceof an SiC crystal containing aluminum atoms, wherein the density ofaluminum atoms is in a range from at least 5E17 cm⁻³ up to 1E19 cm⁻³, byway of example and wherein the scale of the resistance is a logarithmicone. As a consequence of the deep acceptor energy level of aluminum ofabout 200 meV, aluminum atoms not completely ionize at the lower end ofthe operational temperature range. With increasing temperature the holeconcentration increases to a degree that the conductivity in the dopedSiC crystal increases despite decreasing mobility of holes withincreasing temperature.

FIGS. 5A to 5B illustrate the effect of the compensation structure 450of FIG. 4A for a functional semiconductor device with a blockingcapability of 650 V and a total chip area of 4 mm² and take into accounteffects of both the transistor cells and other structures such astermination constructions and gate connections. A center-to-centerdistance between neighboring transistor cells is in a range from, e.g.,2.5 μm to 6.5 μm.

In FIG. 5A line 721 shows, at logarithmic scale, the total C_(gd) as afunction of V_(DS) at a temperature T1=−40° C., line 722 at atemperature T2=25° C. and line 723 at a temperature T3=100° C. At ablocking voltage of 300 V, C_(gd) at −40° C. is about 2.5 times theC_(gd) at 100° C. Since the contribution of the transistor cells toC_(gd) does not change with the temperature as shown in FIG. 3C, thetemperature dependency exclusively results from the compensationstructure 450.

In FIG. 5B line 731 plots V_(GS) as a function of Q_(G) for atemperature T1=−40° C., line 732 for a temperature T2=25° C., and line733 for a temperature T3=100° C. The relative change of V_(th) and, as aconsequence, of Q_(th) is significantly smaller than in FIG. 3A.

FIGS. 6A and 6B refer to an embodiment of a semiconductor device 500 inwhich the compensation structure 450 includes portions of a gatemetallization 330, which may be a gate pad or gate runner. Thesemiconductor device 500 may be or may include an IGFET, for example anMOSFET, an IGBT or an MCD and includes a semiconductor portion 100 witha doped region 180 forming a thermistor structure, a gate metallization330, and an interlayer dielectric 210 separating the gate metallization330 from the semiconductor portion 100 as described in detail withreference to FIG. 4A.

The semiconductor device 500 further includes transistor cells TC formedin the semiconductor portion 100 along trench gate structures 150 whichextend from the first surface 101 into the semiconductor portion 100,wherein mesa sections 170 of the semiconductor portion 100 separateneighboring trench gate structures 150.

A longitudinal extension of the trench gate structures 150 along a firsthorizontal direction may be greater than a transverse extension along asecond horizontal direction orthogonal to the first horizontaldirection. The trench gate structures 150 may be long stripes extendingfrom one side of a transistor cell region to an opposite side, whereinthe length of the trench gate structures 150 may be up to severalmillimeters. According to other embodiments a plurality of separatedtrench gate structures 150 may be arranged along a line extending fromone side of the transistor cell region to the opposite side, or thetrench gate structures 150 may form a grid with the mesa sections 170formed in the meshes of the grid.

The trench gate structures 150 may be equally spaced, may have equalwidth, and may form a regular pattern, wherein a pitch (center-to-centerdistance) of the trench gate structures 150 may be in a range from 1 μmto 10 μm, e.g., from 2 μm to 5 μm. A vertical extension of the trenchgate structures 150 may be in a range from 0.3 μm to 5 μm, e.g., in arange from 0.5 μm to 2 μm.

The trench gate structures 150 include a conductive gate electrode 155which may include or consist of a heavily doped polycrystalline siliconlayer and/or a metal-containing layer. The trench gate structures 150further include a gate dielectric 151 separating the gate electrode 155from the semiconductor portion 100 along at least one side of the trenchgate structure 150. The gate dielectric 151 may include or consist of asemiconductor dielectric, for example thermally grown or depositedsemiconductor oxide, e.g., silicon oxide, a semiconductor nitride, forexample deposited or thermally grown silicon nitride, a semiconductoroxynitride, for example silicon oxynitride, any other depositeddielectric material or any combination thereof. The gate dielectric 151may be formed for a threshold voltage of the transistor cells TC in arange from 1.5 V to 6 V.

The trench gate structures 150 may exclusively include the gateelectrode 155 and the gate dielectric 151 or may include furtherconductive and/or dielectric structures in addition to the gateelectrode 155 and the gate dielectric 151, e.g., compensationstructures.

The trench gate structures 150 may be vertical to the first surface 101or may taper with increasing distance to the first surface 101. Forexample, a taper angle of the trench gate structures 150 with respect tothe vertical direction may be equal to the off-axis angle or may deviatefrom the off-axis angle by not more than ±1 degree such that at leastone of two opposite mesa sidewalls is formed by a crystal planeproviding high charge carrier mobility.

The mesa sections 170 include source zones 110 that are oriented to thefront side and that directly adjoin to at least one of the sidewalls ofthe respective mesa section 170. In the mesa section 170, the sourcezones 110 may directly adjoin to the first surface 101, may directlyadjoin to the opposite mesa sidewall or may be spaced from the oppositemesa sidewall.

The mesa sections 170 further include body zones 115 that separate thesource zones 110 from a drain structure 120, wherein the body zones 115form first pn junctions pn1 with the drain structure 120 and second pnjunctions pn2 with the source zones 110. The body zones 115 directlyadjoin to one mesa sidewall or may directly adjoin to both mesasidewalls. The gate dielectric 151 capacitively couples portions of thebody zones 115 with the gate electrode 155. Both the source zones 110and the body zones 115 are electrically connected to a source electrode310 at the front side. A vertical extension of the body zones 115corresponds to a channel length of the transistor cells TC and may be ina range from 0.2 μm to 1.5 μm.

The semiconductor portion 100 may further include diode regions 116forming third pn junctions pn3 with the drain structure 120. The dioderegions 116 are electrically connected or coupled to the sourceelectrode 310 and may vertically overlap with the trench gate structures150 such that portions of the diode regions 116 are formed in thevertical projection of the trench gate structures 150 and shield activeportions of the gate dielectric 151 against the high potential of thedrain electrode 320 in a blocking state of the semiconductor device 500.The diode regions 116 form third pn junctions pn3 with the drainstructure 120 and provide a fly back diode functionality integrated inthe semiconductor device 500. A distance between opposing edges ofneighboring diode regions 116 may be in a range from 2 μm to 3 μm, byway of example.

The drain structure 120 is oriented to the back, may directly adjoin tothe second surface 102 and is electrically connected or coupled to adrain electrode 320 through an ohmic contact. The drain structure 120may include a lightly doped drift zone 121 that may form the first andthird pn junctions pn1, pn3 as well as the pn junction pnx with thedoped region 180 and may further include a heavily doped contact layer129 between the drift zone 121 and the second surface 102.

The net dopant concentration in the drift zone 121 may be in a rangefrom 1E14 cm⁻³ to 3E16 cm⁻³ in case the semiconductor portion 100 isformed from silicon carbide. A mean dopant concentration in the contactlayer 129 is sufficiently high to ensure an ohmic contact with the drainelectrode 320 that directly adjoins to the second surface 102. In casethe semiconductor device 500 is an MCD or an IGFET, the contact layer129 has the same conductivity type as the drift zone 121. In case thesemiconductor device 500 is an IGBT, the contact layer 129 has thecomplementary conductivity type of the drift zone 121 or includes zonesof the complementary conductivity type.

The drain structure 120 may also include current spread zones 125 whichmay directly adjoin to the body zones 115. The current spread zones 125may extend between neighboring diode regions 116, wherein unipolarhomojunctions between the current spread zones 125 and the drift zone121 may have a greater distance to the first surface 101 than the thirdpn junctions pn3 formed between the diode regions 116 and the drift zone121. Portions of the current spread zones 125 may overlap with thevertical projection of the diode regions 116 and may extend betweenneighboring diode regions 116.

A mean net dopant concentration in the current spread zones 125 is atleast ten times as high as a mean net dopant concentration in the driftzone 121. The reduced horizontal resistance of the current spread zones122 laterally spreads an on-state current of the transistor cells TCsuch that a current distribution in the drift zone 121 is more uniform.

Each of the source electrode 310, the gate metallization 330 and thedrain electrode 320 may consist of or contain, as main constituent(s),aluminum (Al), copper (Cu), or alloys of aluminum or copper such asAlSi, AlCu or AlSiCu. According to other embodiments, at least one ofthe source and drain electrodes 310, 320 may contain, as mainconstituent(s), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta),vanadium (V), silver (Ag), gold (Au), tin (Sn), platinum (Pt), and/orpalladium (Pd). One of the source and drain electrodes 310, 320 or bothmay include two or more sub-layers, wherein each sub-layer contains oneor more of Ni, Ti, V, Ag, Au, W, Sn, Pt, and Pd as main constituent(s),e.g., a silicide, a nitride and/or an alloy.

For example, the source electrode 310 and the gate metallization 330 mayinclude a thin metal-containing interface layer 341 of titanium and amain layer 342 of, e.g., aluminum, copper, nickel or a combination orcompound thereof.

The source electrode 310 may form or may be electrically connected orcoupled to a source terminal S. The drain electrode 320 may form or maybe electrically connected to a drain terminal D and the gatemetallization 330 may form or may be electrically coupled or connectedto a gate terminal G.

According to an embodiment, the transistor cells TC are n-channel FETcells of the enhancement type with p-doped body zones 115 and n-dopedsource zones 110, wherein the diode regions 116 are p-doped and thedrift zone 121 is n-doped. According to another embodiment, thetransistor cells TC are p-channel FET cells of the enhancement type withn-doped body zones 115 and p-doped source zones 110, wherein the dioderegions 116 are n-doped and the drift zone 121 is p-doped.

When a potential at the gate electrode 155 exceeds or falls below athreshold voltage of the semiconductor device 500, minority chargecarriers in the body zones 115 form inversion channels connecting thesource zones 110 with the drain structure 120, thereby turning on thesemiconductor device 500. In the on-state, the load current flowsthrough the semiconductor portion 100 approximately along the verticaldirection between the source and drain electrodes 310, 320.

First contact structures 315 extend from the source electrode 310through openings in the interlayer dielectric 210 to the semiconductorportion 100 and directly adjoin to the source zones 110 and the dioderegions 116. According to the illustrated embodiment the first contactstructures 315 end on the first surface 101. According to otherembodiments, the first contact structures 315 may extend into thesemiconductor portion 100. Second contact structures 316 extend throughthe interlayer dielectric 210 and electrically connect the sourceelectrode 310 with the doped region 180.

According to other embodiments, the layout of the transistor cell fieldmay include symmetric transistor cells with the source and body zonesformed symmetric to a longitudinal center axis of the trench gatestructures. According to other embodiments, the diode regions are formedseparated from the first surface and contacts splitting the trench gatestructures in half trench structures electrically connect the dioderegions with the source electrode. Alternatively or in addition,transistor cells may alternate with other structures, e.g., dioderegions along two orthogonal horizontal directions. The gate structures150 may be planar gates formed outside of the semiconductor portion 100,wherein the gate dielectric 151 may be formed directly adjoining to orat least parallel to the first surface 101.

The semiconductor device 500 of FIG. 7 includes a semiconductor portion100 with an outer lateral surface 103 and with a plurality of stripeshaped trench gate structures 150. Two stripe shaped gate runners 332run orthogonal to the gate trench structures 150. A rectangular gate pad331 is formed in a rectangular opening of the source electrode 310. Thegate pad 331 overlaps with both gate runners 332 and gate contacts 335that electrically connect the gate runners 332 with the gate pad 331.

A doped region 180 containing aluminum atoms is formed in verticalprojection of the gate pad 331 and may overlap on two opposite sides ofthe gate pad 331 with the source electrode 310. Second contactstructures 316 extend from the source electrode 310 into the dopedregion 180 and electrically connect the doped region 180 with the sourceelectrode 331.

The second contact structures 316 may be stripe shaped or may be dots,may be formed on both sides of the gate pad 331 or at one single side. Alateral extension between a center axis of the gate pad 331 and thesecond contact structures 316 and giving a minimum active horizontalextension of the doped region 180 is significantly greater than a pitchof the gate trench structures 150, for example, in a range from about100 μm to about 500 μm. The active horizontal extension is thatextension along which the compensation voltage drops.

Size and position of the second contact structures 316 relative to thedoped region 180 relate to the resistance value of the doped region 180such that the resistance value of the doped region 180 can be finelyadjusted.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A semiconductor device comprising: transistorcells formed in a semiconductor portion from a wide bandgap material andelectrically connected to a gate terminal, a source terminal and a drainterminal; a compensation structure electrically connected with the gateterminal and at least one of the source terminal and the drain terminal,wherein an effective capacitance of the compensation structure has atemperature coefficient at least partly compensating for a temperaturecoefficient of a ratio between a gate-to-drain capacitance and agate-to-source capacitance of the transistor cells.
 2. The semiconductordevice of claim 1, wherein the compensation structure comprises a firstcapacitive structure with a first capacitance effective between thedrain terminal and the gate terminal and wherein the first capacitancehas a negative temperature coefficient.
 3. The semiconductor device ofclaim 1, wherein the compensation structure includes a second capacitivestructure with a capacitance effective between the gate terminal and thesource terminal and wherein the capacitance has a positive temperaturecoefficient.
 4. The semiconductor device of claim 1, wherein thecompensation structure comprises a series connection of a firstcapacitive structure and a second capacitive structure between the gateterminal and the drain terminal, and a thermistor structure with anegative temperature coefficient between the source terminal and aconnection node between the first and second capacitive structures. 5.The semiconductor device of claim 4, wherein the thermistor structurecomprises a doped region in the semiconductor portion.
 6. Thesemiconductor device of claim 5, wherein the doped region containsaluminum at a concentration of at least 5E17 cm³.
 7. The semiconductordevice of claim 5, further comprising: a contact structure extendingthrough an interlayer dielectric and electrically connecting a sourceelectrode with the doped region, wherein the interlayer dielectricseparates the source electrode and the semiconductor portion.
 8. Thesemiconductor device of claim 5, wherein a first electrode of the firstcapacitive structure is a portion of a gate metallization separated fromthe semiconductor portion by a portion of an interlayer dielectric. 9.The semiconductor device of claim 8, wherein a gate pad forms the firstelectrode of the first capacitive structure.
 10. The semiconductordevice of claim 5, wherein the doped region forms a second electrode ofthe first capacitive structure, the connection node and a firstelectrode of the second capacitive structure.
 11. The semiconductordevice of claim 5, further comprising: a drain structure in thesemiconductor portion, the drain structure electrically connecting thetransistor cells with a drain electrode, the drain structure forming apn junction with the doped region and forming a second electrode of thesecond capacitive structure.
 12. A semiconductor device comprising:transistor cells in a semiconductor portion from silicon carbide,wherein the transistor cells are electrically connected to a gatemetallization, a source electrode and a drain electrode; a doped regionin the semiconductor portion, wherein the doped region is electricallyconnected to the source electrode and a resistance of the doped regionhas a negative temperature coefficient; an interlayer dielectricseparating the gate metallization from the doped region; a drainstructure in the semiconductor portion, wherein the drain structureelectrically connects the transistor cells with the drain electrode andforms a pn junction with the doped region.
 13. The semiconductor deviceof claim 12, wherein the doped region contains aluminum at aconcentration of at least 5E17 cm⁻³.
 14. The semiconductor device ofclaim 12, further comprising: a contact structure extending through theinterlayer dielectric and directly adjoining to the source electrode andthe doped region.
 15. The semiconductor device of claim 14, wherein twoof the contact structures are arranged at opposite sides of the gatemetallization.
 16. The semiconductor device of claim 12, wherein thegate metallization comprises a gate pad.
 17. The semiconductor device ofclaim 12, wherein the doped region has a minimum active horizontalextension of at least 100 μm.
 18. The semiconductor device of claim 12,wherein the doped region directly adjoins to a first surface of thesemiconductor portion.
 19. The semiconductor device of claim 12, whereinthe drain structure includes a heavily doped contact layer and a lightlydoped drift zone forming the pn junction with the doped region andseparating the doped region from the contact layer.
 20. A semiconductordevice comprising: transistor cells in a semiconductor portion fromsilicon carbide, wherein the transistor cells are electrically connectedto a gate metallization, a source electrode and a drain electrode; adoped region in the semiconductor portion, wherein the doped region iselectrically connected to the source electrode and a resistance of thedoped region has a negative temperature coefficient; an interlayerdielectric separating the gate metallization from the doped region; adrain structure in the semiconductor portion, wherein the drainstructure electrically connects the transistor cells with the drainelectrode and forms a pn junction with the doped region; a contactstructure extending through the interlayer dielectric and directlyadjoining to the source electrode and the doped region; the doped regiondirectly adjoins to a first surface of the semiconductor portion; andthe drain structure includes a heavily doped contact layer and a lightlydoped drift zone forming the pn junction with the doped region andseparating the doped region from the contact layer.